Integrated circuits (chips or die) typically comprise a semiconductor substrate and semiconductor devices, such as transistors and resistors, formed from doped regions within the substrate. Interconnect structures (also referred to as metallization layers), formed in electrically isolated layers overlying the substrate provide electrical connection between doped regions to form electrical circuits in the integrated circuit. To provide physical and environmental protection, most integrated circuits are enclosed in a package having a plurality of externally directed pins or leads through which the integrated circuit is connected to other electrical components. In certain applications, the chip is direct-mounted to a receiving structure, such as a printed circuit board that carriers other electronic components, without the use a package; i.e., a bare die. Other mounting technologies are known to those skilled in the art, including epoxy underfill.
Current flow through the chip devices and the interconnect structures generates heat, raising the internal temperature of the chip and its constituent elements. Whether the chip is packaged or used as a bare die, the heat should be removed from the chip, either through the substrate or the metallization layers, to maintain a chip operating temperature below a predetermined temperature limit.
Excessive chip temperatures can cause temporary or permanent alterations in chip operation. Permanent changes lead to premature chip failure and thus are considered chip reliability failures. Temporary changes affect functional performance during the interval of excessive temperature, but the integrated circuit returns to normal functionality after the temperature falls to its nominal design value.
For chip reliability failures, excessive operational temperatures exponentially decrease chip lifetime. Electromigration and silicon dioxide breakdown, either of which can lead to chip failure, both worsen with increased temperature. At higher temperatures corrosion mechanisms accelerate and increased differential thermal expansion stresses are generated at material interfaces, such as the interfaces between semiconductor materials and metal interconnect structures.
To avoid performance or functional effects resulting from excessive temperatures, an integrated circuit is designed to operate below an upper temperature limit. The actual operating temperature is influenced by ambient temperature, the chip's operating speed, and the supply voltage. Temperatures above the design limit can cause device instability, and regions of differential temperature within the chip can cause mismatched operation of matched components. The reverse bias current in pn junctions, such as the pn junctions of diodes, bipolar junction transistors (BJT's) and metal-oxide semiconductor field effect transistors (MOSFET's) increases with increasing temperature, affecting device performance.
If an element within the chip dissipates a substantial amount of power, occupies a relatively small area, or is on a thermal path that includes a high thermal resistance to the ambient environment, the device may experience a substantial temperature rise. For example, consider a polysilicon resistor for biasing a high-current circuit. Such resistors are typically very small and are formed over an isolation layer comprising silicon dioxide, which presents a relatively high thermal resistance in the thermal path from the resistor to the semiconductor substrate. Thus the temperature rise in a local region proximate the resistor can be very high, reducing the lifetime of the resistor and surrounding components.
To reduce the chip's operating temperature, it is known to use a passive heat sink attached to a bottom surface of the chip to more efficiently transfer heat from the chip to the ambient environment. FIG. 1 illustrates a device package 1 comprising package leads 2. An integrated circuit 4 and a heat sink 5 underlying a bottom surface of the integrated circuit 4, are affixed within a die attach area 6. Bond pads 7 are formed on an upper surface 8 of the integrated circuit 4, and connected to the package leads 2 by bond wires 9.
In another known package structure, referred to as flip-chip or bump bonding, the bond wires 9 of FIG. 1 are replaced with deposited solder bumps 10 formed on the bond pads 7. See FIG. 2. The integrated circuit 4 is connected to a package by flipping the integrated circuit 4 and soldering the bumps 10 to corresponding package receiving pads that are in turn connected to corresponding package leads.
According to both packaging structures described above, heat is withdrawn from the integrated circuit 4 through thermal paths to the heat sink 5. A metal plate, referred to as a copper slug, is one example of such a heat sink. Because the semiconductor substrate is a better thermal conductor than most other materials within the chip (with the exception of the electrically conductive interconnect structures), it is preferred to direct heat through the substrate to the heat sink 5. The thermal conductivity of materials comprising the chip varies widely. The thermal conductivity of copper is about 4.0 W/cm-°K, silicon is about 1.5 W/cm-°K and silicon dioxide is about 0.01 W/cm-°K. It is also possible, but not necessarily desirable, to direct heat through silicon dioxide regions within the chip. Prior to attaching the heat sink 5 to the integrated circuit 4, a back-grinding process thins a bottom surface of the semiconductor substrate to increase thermal conductivity to the heat sink 5 by shortening the thermal path through the substrate.
When packaged in the package 1 of FIG. 1, heat flows from the heat sink 5 into the package 1,which may further include a package heat sink (not shown) to improve heat dissipation from the package to the ambient environment. To further improve heat dissipation, a cooling fan mounted proximate the package directs ambient air across the package heat sink.
It is also possible to conduct heat through the chip to a top surface of the integrated circuit 4. However, this is generally not the preferred primary heat removal path due to the presence of the bond pads 7 and electrical conductive connections to the bond pads 7 that may interfere with and reduce the effectiveness of a heat sink mounted to the top surface. However, the chip's top surface can serve as a secondary heat sink. Some heat generated by power-dissipating elements within the chip flows upwardly through the chip interconnect structures and away from the chip through the bond wires 9 or the solder bumps 10.
Both the capacity of the heat removal mechanism and the operational effects of high device operating temperatures must be considered during chip design. However, design tools for evaluating thermal constraints are not widely available and are poorly integrated into the chip design process. If it is determined that the ratio of power density to thermal conductivity in a chip is above a predetermined threshold, to avoid potential thermal problems the chip must be redesigned to lower the power density or increase the thermal conductivity. One known technique for increasing thermal conductivity lowers the thermal resistance between the heat dissipating components and a surface of the semiconductor substrate, where a heat sink can be disposed if desired. The back-grinding process described above is such a technique.
Although it is axiomatic that thermal conductivity improvements must not degrade device performance, certain prior art attempts to improve heat flow to the heat sink have unfortunately constrained device design. For example, high-power dissipation circuit elements should not be surrounded by a high-thermal resistance material. Thus polysilicon resistors disposed overlying silicon dioxide are avoided and substrate resistors (i.e., resistors formed from doped regions in the semiconductor substrate) are employed instead. Although improving thermal conductivity for resistor-generated heat, this technique reduces design flexibility. Since the semiconductor substrate has a higher thermal conductivity than silicon dioxide, heat generated by a substrate resistor flows through a higher thermal conductivity path to a chip surface. However, substrate resistors have far higher parasitic leakage and capacitance than a polysilicon resistor formed in a silicon dioxide layer. The resistance of the substrate resistor also exhibits a greater dependency on the applied voltage than a polysilicon resistor, and may generate more noise.
If the power dissipation of a chip exceeds design limits, it may be necessary to redesign the chip, such as by increasing device area. Although increasing the device area reduces power dissipation in a volume of chip material, the chip area and costs are increased. A larger device area can also increase parasitic capacitance and device power consumption. Another device design strategy reduces power dissipation by altering one or more performance specification of the integrated circuit, e.g., reducing the device's operating voltage or operating speed. Although this may be acceptable for certain device applications, generally product manufacturers demand higher speed integrated circuits.
As development of VLSI and ULSI (very large scale and ultra large scale) integrated circuits continues, device size shrinks, device density increases and digital device clock speed increases. These technology advances exacerbate concerns over excessive operating temperatures within the integrated circuit due to marginal or inadequate heat removal mechanisms.